
16 Mbit Multi-Purpose Flash Plus
A Microchip Technology Company
SST39WF1601 / SST39WF1602
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T BP
ADDRESS A19-0
5555
2AAA
5555
ADDR
CE#
T AH
T CP
T DH
T AS
T CPH
T DS
OE#
T CH
WE#
T CS
DQ15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
Note: WP# must be held in proper logic state (V IL or V IH ) 1 μs prior to and 1μs after the command sequence.
X can be V IL or V IH, but no other value.
Figure 6: CE# Controlled Program Cycle Timing Diagram
ADDRESS A 19-0
T C E
CE#
T OEH
OE#
T OE
WE#
1297 F05.1
T OES
DQ 7
DATA
DATA#
DATA#
DATA
1297 F06.1
Figure 7: Data# Polling Timing Diagram
?2011 Silicon Storage Technology, Inc.
19
DS-25014A
04/11